Senior IC Verification Engineer - Leuven, Belgium - ...

Senior IC Verification Engineer

Initial 6 month freelance contract + extensions

Leuven, Belgium (3 days onsite per week)

40 hours / week

ASAP start

Top 3 must have skills: UVM, SystemVerilog, Assertion-based Verification

Responsibilities:

- Own the verification of a block, some subsystem part or some top level functions

- Detail the verification specification of the assigned testcases

- Implement the testcases using System Verilog, UVM, Python, assertions

- Maximize the verification coverage of the design while focusing on execution time

- Maintain the regression suite

- Execute to meet challenging schedule while ensuring high quality

- Participate actively in peer reviews

- Interface with architects during design reviews, root-cause analysis and correction of issues

- Work within a design and/or verification team, and interact with other teams on the project (Analog, Firmware, Layout) to ensure the success of the overall product

Profile:

- Master Degree in Electronic/Electrical Engineering

- Minimum of 5 years experience in the design and/or verification of digital blocks and IC’s

- Knowledge of low power design techniques

- Knowledge of audio processing and/or accelerators for artificial intelligence is a plus

- Proven track record in delivering working silicon for high volume products

- Demonstrate an innovative and creative attitude, taking initiative to propose and implement improvements

- Rigorous and methodical with good analytical skills for debugging issues in design and on silicon

- Familiarity with Cadence EDA simulation tools and Synopsys Spyglass

- Expert in VHDL, Verilog and/or SystemVerilog. Knowledge and experience of python programming language is an asset

- You are a team player with excellent communication skills adapted to an international environment.

- You possess a hands on practical skills combined with electrical knowledge.

- You are fluent in English.