Responsibilities:
_Own the verification of a block, some subsystem part or some top level functions
_Detail the verification specification of the assigned testcases
_Implement the testcases using System Verilog, UVM, Python, assertions
_Maximize the verification coverage of the design while focusing on execution time
_Maintain the regression suite
_Execute to meet challenging schedule while ensuring high quality
_Participate actively in peer reviews
_Interface with architects during design reviews, root-cause analysis and correction of issues
_Work within a design and/or verification team, and interact with other teams on the project (Analog, Firmware, Layout) to ensure the success of the overall product
Profile:
_Master Degree in Electronic/Electrical Engineering
_Minimum of 5 years experience in the design and/or verification of digital blocks and IC’s
_Knowledge of low power design techniques
_Knowledge of audio processing and/or accelerators for artificial intelligence is a plus
_Proven track record in delivering working silicon for high volume products
_Demonstrate an innovative and creative attitude, taking initiative to propose and implement improvements
_Rigorous and methodical with good analytical skills for debugging issues in design and on silicon
_Familiarity with Cadence EDA simulation tools and Synopsys Spyglass
_Expert in VHDL, Verilog and/or SystemVerilog. Knowledge and experience of python programming language is an asset
_You are a team player with excellent communication skills adapted to an international environment.
_You possess a hands on practical skills combined with electrical knowledge.
_You are fluent in English.